`timescale 1ns / 1ps
module pc(pcout,pcin,writepc,clk,rst);
input clk,rst;
input writepc;
input pcin;
output pcout;
wire [4:0]pcin;
reg [4:0]pcout;
wire writepc;

always @(posedge clk or negedge rst) begin  
    if (!rst) 
        pcout <= 32'd0;  
    else 
	   begin
		  if(writepc)
					 pcout<=pcin;
		  else 
					 pcout<=pcout;
	   end
end
endmodule
